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  • Phase-locked loop (PLL) clock generator

155.52, 622.08 Mbps, 77.76, - 155.52 MHz | S1212

Article: 00024551

Phase-locked loop (PLL) clock generator

* Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer, and jitter generation
* On-chip high-frequency PLLs for clock generation and clock recovery
* Supports clock recovery for 155.52 Mbps (OC-3) and 622.08 Mbps (OC-12)
* Selectable reference frequencies of 77.76 or 155.52 MHz
* Directly compatible with 2.5 V or 3.3 V LVDS, 3.3 V LVPECL (DC and AC)
* 196 plastic ball grid array package
* 1.2 V and 3.3 V/2.5 V supply
* Lock detect
* Signal detect input (SD[3:0])
* Typical 385 mW power in LVDS mode
* Internal termination to the OPTICs LVPECL driver rendering seamless connection and saving a total of 235 mW at the system level
* Quad configuration, mixed OC-3/OC-12
* CMOS 0.13 micron technology


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